Pipeline ADCs are employed is in wide variety of applications, such as for signal processing in the field of video and communication. An example of a conventional circuit is Japanese Patent Application No. JP10-163,875. In many of these applications, in order to decrease power consumption by the signal processor, the frequency of the clock signal is switched. For example, when pictures are taken and recorded to a memory in a digital camera, in order to increase the resolution of the pictures, the frequency of the clock signal is increased, and the clock signal is decreased to lower the resolution of the image only in the period when the image of the object is displayed on the screen. That way, switching the frequency of the clock signal to correspond to the user's application mode or the like, it is possible to efficiently decrease the current consumption, particularly of the logic circuit. However, a pipeline ADC is a circuit with combined analog and digital portions, and the current steadily consumed by the analog portion is larger than that consumed in the digital portion. The method for switching the frequency of the clock signal is effective in decreasing the current flowing any time the logic value of the output of the digital portion varies. However, this method has no effect at all in decreasing the current steadily consumed in the analog portion.